Bachelor degree or above, over 1 year experience of practical RTL design, FPGA practice or back-end experience, rigorous debug logic thinking, strong practical ability in simulation and verification, solid professional knowledge of synchronous sequence and time domain switching analysis, good understanding in synchronous and modular design of the complex state machine; Acknowledge the process from RTL to gate level, familiar with Verilog Coding, Synthesis/Timing verification, FPGA flow and several aspects of the test; preferable in knowing the following aspects: SOC AHB/AXI bus setup, matlab/simulink modeling, digital fixed point filter design, audio & video interface, ATPG DFT, DDR, USB, HDMI, RFID and digital signal processing. Future work involves the design of next generation high speed interface protocol design, high performance

Bachelor degree or above, over 1 year experience of practical RTL design, FPGA practice or back-end experience, rigorous debug logic thinking, strong practical ability in simulation and verification, solid professional knowledge of synchronous sequence and time domain switching analysis, good understanding in synchronous and modular design of the complex state machine; Acknowledge the process from RTL to gate level, familiar with Verilog Coding, Synthesis/Timing verification, FPGA flow and several aspects of the test; preferable in knowing the following aspects: SOC AHB/AXI bus setup, matlab/simulink modeling, digital fixed point filter design, audio & video interface, ATPG DFT, DDR, USB, HDMI, RFID and digital signal processing. Future work involves the design of next generation high speed interface protocol design, high performance